Design a Synchronous Base-12 Counter Using D Flip-flops
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Design a mod-12 Synchronous up counter. Ans. Design of a mod 12 synchronous counter by using D-flipflops. I state table A B C D A B C D DA DB DC DD 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0
Present state Next state Required D Inputs
Firstly draw the state table containing present state, subsequent state and required flip-flop input to provide the transition. D flip flop offers the output similar as the next state itself. After that, solve through using K maps to determine DA DB DC DD for all states.
Unutilized states are 1100,1101,1110,1111 they can be function as don't care conditions from the table. Depict Karnaugh-maps for DA, DB, DC and DD as follows and acquire Boolean expressions for them. 
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Design a Synchronous Base-12 Counter Using D Flip-flops
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